Code generation tool for control and status registers

AMBA AXI VIP

An AXI4 crossbar implementation in SystemVerilog

Network on Chip Implementation written in SytemVerilog

Control and status register code generator toolchain

Education kit for teaching introductory Arm-based system-on-chip design on FPGA with lectures and practical labs (educational)

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

Education kit for teaching advanced Arm Cortex-A system-on-chip design on FPGA platforms with lectures and hands-on labs (educational)

Education kit for teaching efficient embedded systems design on Arm Cortex-M platforms with labs and lecture materials (educational)

AHB3-Lite Interconnect

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

Textbook on system-on-chip design using Arm Cortex-M microcontrollers covering AMBA, peripherals, and embedded software (educational)

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

Reference book for SoC and FPGA designers integrating Arm Cortex-M processors with AMBA bus architectures (educational)

Verification IP for AMBA APB Protocol

Open-source AMBA CHI infrastructures (supporting Issue B, E.b)

Master and Slave made using AMBA AXI4 Lite protocol.

Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.

Multi-Technology RAM with AHB3Lite interface

APB master and slave developed in RTL.